Reorda, M. S.: search on Z-Library

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1

An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits

P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante

Journal:

Journal of Electronic Testing

Year:

2002

Language:

english

File:

PDF, 198 KB

english, 2002

2

[IEEE 2017 18th IEEE Latin American Test Symposium (LATS) - Bogota, Colombia (2017.3.13-2017.3.15)] 2017 18th IEEE Latin American Test Symposium (LATS) - An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standard

Bagalini, E., Sini, J., Reorda, M. Sonza, Violante, M., Klimesch, H., Sarson, P.

Year:

2017

Language:

english

File:

PDF, 239 KB

english, 2017

3

[IEEE 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) - Platja d'Aro (2018.7.2-2018.7.4)] 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) - Towards an automatic approach for hardware verification according to ISO 26262 functional safety standard

Sini, J., Sonza Reorda, M., Violante, M., Sarson, P.

Year:

2018

Language:

english

File:

PDF, 112 KB

english, 2018

4

[IEEE 2020 IEEE 38th VLSI Test Symposium (VTS) - San Diego, CA, USA (2020.4.5-2020.4.8)] 2020 IEEE 38th VLSI Test Symposium (VTS) - Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks

da Silva, Felipe Augusto, Cagri Bagbaba, Ahmet, Ruospo, Annachiara, Mariani, Riccardo, Kanawati, Ghani, Sanchez, Ernesto, Reorda, Matteo Sonza, Jenihhin, Maksim, Hamdioui, Said, Sauer, Christian

Year:

2020

File:

PDF, 315 KB

2020

5

A Parallel Tester Architecture for Accelerometer and Gyroscope MEMS Calibration and Test

Lyl M. Ciganda Brasca, Paolo Bernardi, Matteo Sonza Reorda, Dimitri Barbieri, Luciano Bonaria, Roberto Losco, Luciano Marcigot, Maurizio Straiotto

Journal:

Journal of Electronic Testing

Year:

2011

Language:

english

File:

PDF, 897 KB

english, 2011

6

Functional Verification of DMA Controllers

Michelangelo Grosso, Wilson Javier Perez Holguin, Danilo Ravotto, Ernesto Sanchez, Matteo Sonza Reorda, Alberto Tonda, Jaime Velasco Medina

Journal:

Journal of Electronic Testing

Year:

2011

Language:

english

File:

PDF, 359 KB

english, 2011

7

Microprocessor Software-Based Self-Testing

Psarakis, M., Gizopoulos, D., Sanchez, E., Reorda, M.S.

Journal:

IEEE Design & Test of Computers

Year:

2010

Language:

english

File:

PDF, 1.12 MB

english, 2010

8

Integrating online and offline testing of a switching memory

Barbagallo, S., Medina, D., Corno, F., Prinetto, P., Reorda, M.S.

Journal:

IEEE Design & Test of Computers

Year:

1998

Language:

english

File:

PDF, 127 KB

english, 1998

9

Automatic test program generation: a case study

Corno, F., Sanchez, E., Reorda, M.S., Squillero, G.

Journal:

IEEE Design & Test of Computers

Year:

2004

Language:

english

File:

PDF, 289 KB

english, 2004

10

A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

Mohammadi, Hassan Ghasemzadeh, Gaillardon, Pierre-Emmanuel, Zhang, Jian, Micheli, Giovanni De, Sanchez, Ernesto, Reorda, Matteo Sonza

Journal:

ACM Journal on Emerging Technologies in Computing Systems

Year:

2016

Language:

english

File:

PDF, 754 KB

english, 2016

11

[IEEE 2020 IEEE European Test Symposium (ETS) - Tallinn, Estonia (2020.5.25-2020.5.29)] 2020 IEEE European Test Symposium (ETS) - Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs

da Silva, Felipe Augusto, Bagbaba, Ahmet Cagri, Sartoni, Sandro, Cantoro, Riccardo, Reorda, Matteo Sonza, Hamdioui, Said, Sauer, Christian

Year:

2020

File:

PDF, 290 KB

2020

12

Identification and classification of single-event upsets in the configuration memory of sram-based fpgas

Ceschia, M., Violante, M., Reorda, M.S., Paccagnella, A., Bernardi, P., Rebaudengo, M., Bortolato, D., Bellato, M., Zambolin, P., Candelori, A.

Journal:

IEEE Transactions on Nuclear Science

Year:

2003

Language:

english

File:

PDF, 316 KB

english, 2003

13

RT-level ITC'99 benchmarks and first ATPG results

Corno, F., Reorda, M.S., Squillero, G.

Journal:

IEEE Design & Test of Computers

Year:

2000

Language:

english

File:

PDF, 118 KB

english, 2000

14

A new hybrid fault detection technique for systems-on-a-chip

Bernardi, P., Bolzani, L.M.V., Rebaudengo, M., Reorda, M.S., Vargas, F.L., Violante, M.

Journal:

IEEE Transactions on Computers

Year:

2006

Language:

english

File:

PDF, 1.21 MB

english, 2006

15

[IEEE 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012) - Dresden (2012.03.12-2012.03.16)] 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE) - A new SBST algorithm for testing the register file of VLIW processors

Sabena, D., Reorda, M. S., Sterpone, L.

Year:

2012

Language:

english

File:

PDF, 463 KB

english, 2012

16

[IEEE Conference Publications Design Automation and Test in Europe - Dresden, Germany (2014.03.24-2014.03.28)] Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014 - GPGPUs: How to combine high computational power with high reliability

Gomez, L. Bautista, Cappello, F., Carro, L., DeBardeleben, N., Fang, B., Gurumurthi, S., Pattabiraman, K., Rech, P., Reorda, M. Sonza

Year:

2014

Language:

english

File:

PDF, 389 KB

english, 2014

17

Software-Based Hardening Strategies for Neutron Sensitive FFT Algorithms on GPUs

Pilla, L. L., Rech, P., Silvestri, F., Frost, C., Navaux, P. O. A., Reorda, M. Sonza, Carro, L.

Journal:

IEEE Transactions on Nuclear Science

Year:

2014

Language:

english

File:

PDF, 925 KB

english, 2014

18

[IEEE 2013 Design and Test Symposium (IDT) - Marrakesh, Morocco (2013.12.16-2013.12.18)] 2013 8th IEEE Design and Test Symposium - On the evaluation of soft-errors detection techniques for GPGPUs

Sabena, D., Reorda, M. Sonza, Sterpone, L., Rech, P., Carro, L.

Year:

2013

Language:

english

File:

PDF, 682 KB

english, 2013

19

[IEEE Comput. Soc Eighth IEEE International High-Level Design Validation and Test Workshop - San Francisco, CA, USA (12-14 Nov. 2003)] Eighth IEEE International High-Level Design Validation and Test Workshop - High-level test generation for hardware testing and software validation

Goloubeva, O., Sonza Reorda, M., Violante, M.

Year:

2003

Language:

english

File:

PDF, 405 KB

english, 2003

20

On the Functional Test of Branch Prediction Units

Sanchez, Ernesto, Reorda, Matteo Sonza

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2014

Language:

english

File:

PDF, 1.64 MB

english, 2014

21

[IEEE 2010 11th Latin American Test Workshop - LATW - Punta del Este, Uruguay (2010.03.28-2010.03.31)] 2010 11th Latin American Test Workshop - Functional test generation for DMA controllers

Grosso, M., Perez H., W. J., Ravotto, D., Sanchez, E., Reorda, M. Sonza, Medina, J. Velasco

Year:

2010

Language:

english

File:

PDF, 203 KB

english, 2010

22

[IEEE Comput. Soc. Press 14th VLSI Test Symposium - Princeton, NJ, USA (28 April-1 May 1996)] Proceedings of 14th VLSI Test Symposium - Scan insertion criteria for low design impact

Barbagallo, S., Lobetti Bodoni, M., Medina, D., Corno, F., Prinetto, P., Sonza Reorda, M.

Year:

1996

Language:

english

File:

PDF, 555 KB

english, 1996

23

[IEEE 2012 21st Asian Test Symposium (ATS) - Niigata, Japan (2012.11.19-2012.11.22)] 2012 IEEE 21st Asian Test Symposium - Peak Power Estimation: A Case Study on CPU Cores

Bernardi, P., De Carvalho, M., Sanchez, E., Reorda, M. Sonza, Bosio, A., Dilillo, L., Girard, P., Valka, M.

Year:

2012

Language:

english

File:

PDF, 755 KB

english, 2012

24

[IEEE Comput. Soc. Press Third IEEE Symposium on Parallel and Distributed Processing - Dallas, TX, USA (2-5 Dec. 1991)] Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing - A parallel system for test pattern generation

Balboni, G.P., Cabodi, G.P., Gai, S., Sismondi, D., Reorda, M.S.

Year:

1991

Language:

english

File:

PDF, 586 KB

english, 1991

25

[IEEE 1998 IEEE International Conference on Evolutionary Computation Proceedings. IEEE World Congress on Computational Intelligence - Anchorage, AK, USA (4-9 May 1998)] 1998 IEEE International Conference on Evolutionary Computation Proceedings. IEEE World Congress on Computational Intelligence (Cat. No.98TH8360) - A new evolutionary algorithm inspired by the selfish gene theory

Corno, F., Reorda, M.S., Squillero, G.

Year:

1998

Language:

english

File:

PDF, 625 KB

english, 1998

26

[IEEE 2013 14th Latin American Test Workshop - LATW - Cordoba (2013.4.3-2013.4.5)] 2013 14th Latin American Test Workshop - LATW - On the functional test of the BTB logic in pipelined and superscalar processors

Changdao, D., Graziano, M., Sanchez, E., Reorda, M. Sonza, Zamboni, M., Zhifan, N.

Year:

2013

Language:

english

File:

PDF, 1.01 MB

english, 2013

27

[IEEE 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems - Liberec, Czech Republic (2009.04.15-2009.04.17)] 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems - An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs

Ciganda, L., Abate, F., Bernardi, P., Bruno, M., Sonza Reorda, M.

Year:

2009

Language:

english

File:

PDF, 435 KB

english, 2009

28

[IEEE 2013 14th International Workshop on Microprocessor Test and Verification (MTV) - Austin, TX, USA (2013.12.11-2013.12.13)] 2013 14th International Workshop on Microprocessor Test and Verification - On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors

Bernardi, P., Cantoro, R., Ciganda, L., Du, B., Sanchez, E., Reorda, M. Sonza, Grosso, M., Ballan, O.

Year:

2013

Language:

english

File:

PDF, 263 KB

english, 2013

29

[ACM Press the eighth international workshop - San Diego, California, United States (2000..-..)] Proceedings of the eighth international workshop on Hardware/software codesign - CODES '00 - Automatic test bench generation for simulation-based validation

Lajolo, M., Lavagno, L., Rebaudengo, M., Reorda, M. Sonza, Violante, M.

Year:

2000

Language:

english

File:

PDF, 163 KB

english, 2000

30

[IEEE 2012 17th IEEE European Test Symposium (ETS) - Annecy, France (2012.05.28-2012.05.31)] 2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS) - On-line software-based self-test of the Address Calculation Unit in RISC processors

Bernardi, P., Ciganda, L., de Carvalho, M., Grosso, M., Lagos-Benites, J., Sanchez, E., Reorda, M. Sonza, Ballan, O.

Year:

2012

Language:

english

File:

PDF, 350 KB

english, 2012

31

[IEEE 2014 IEEE 20th International On-Line Testing Symposium (IOLTS) - Platja d'Aro, Girona, Spain (2014.7.7-2014.7.9)] 2014 IEEE 20th International On-Line Testing Symposium (IOLTS) - Fault injection in GPGPU cores to validate and debug robust parallel applications

De Carvalho, M., Sabena, D., Reorda, M. Sonza, Sterpone, L., Rech, P., Carro, L.

Year:

2014

File:

PDF, 105 KB

2014

32

[IEEE 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010 - Paris, France (2010.05.30-2010.06.2)] Proceedings of 2010 IEEE International Symposium on Circuits and Systems - A novel scalable and reconfigurable emulation platform for embedded systems verification

Di Marzio, M., Grosso, M., Reorda, M. Sonza, Sterpone, L., Audisio, G., Sabatini, M.

Year:

2010

Language:

english

File:

PDF, 270 KB

english, 2010

33

[IEEE 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Amsterdam, Netherlands (2014.10.1-2014.10.3)] 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - On the in-field functional testing of decode units in pipelined RISC processors

Bernardi, P., Cantoro, R., Ciganda, L., Sanchez, E., Reorda, M. Sonza, De Luca, S., Meregalli, R., Sansonetti, A.

Year:

2014

Language:

english

File:

PDF, 190 KB

english, 2014

34

A Flexible Framework for the Automatic Generation of SBST Programs

Riefert, Andreas, Cantoro, Riccardo, Sauer, Matthias, Sonza Reorda, Matteo, Becker, Bernd

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2016

Language:

english

File:

PDF, 1.51 MB

english, 2016

35

[Presses Polytech. Univ. Romandes ISCAS 2000 Geneva. 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings - Geneva, Switzerland (28-31 May 2000)] 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353) - An improved cellular automata-based BIST architecture for sequential circuits

Corno, F., Sonzs Reorda, M., Squillero, G.

Year:

2000

Language:

english

File:

PDF, 436 KB

english, 2000

36

[IEEE 2019 IEEE Latin American Test Symposium (LATS) - Santiago, Chile (2019.3.11-2019.3.13)] 2019 IEEE Latin American Test Symposium (LATS) - On the evaluation of SEU effects in GPGPUs

Du, B., Rodriguez Condia, Josie E., Sonza Reorda, M., Sterpone, L.

Year:

2019

Language:

english

File:

PDF, 1.12 MB

english, 2019

37

Fault Grading Techniques of Software Test Libraries for Safety-Critical Applications

Floridia, Andrea, Sanchez, Ernesto, Sonza Reorda, Matteo

Journal:

Year:

2019

Language:

english

File:

PDF, 40 KB

english, 2019

38

[IEEE 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) - Mykonos, Greece (2019.4.16-2019.4.18)] 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) - An extended model to support detailed GPGPU reliability analysis

Du, B., Condia, Josie E. Rodriguez, Reorda, Matteo Sonza

Year:

2019

Language:

english

File:

PDF, 274 KB

english, 2019

39

[IEEE 2019 IEEE European Test Symposium (ETS) - Baden-Baden, Germany (2019.5.27-2019.5.31)] 2019 IEEE European Test Symposium (ETS) - A Dynamic Greedy Test Scheduler for Optimizing Probe Motion in In-Circuit Testers

Bonaria, L., Raganato, M., Reorda, M. Sonza, Squillero, G.

Year:

2019

Language:

english

File:

PDF, 565 KB

english, 2019

40

[IEEE 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Cluj-Napoca, Romania (2019.4.24-2019.4.26)] 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test

Almeida, F., Bernardi, P., Calabrese, D., Restifo, M., Reorda, M. Sonza, Appello, D., Pollaccia, G., Tancorre, V., Ugioli, R., Zoppi, G.

Year:

2019

Language:

english

File:

PDF, 473 KB

english, 2019

41

[IEEE 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Noordwijk, Netherlands (2019.10.2-2019.10.4)] 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Challenges of Reliability Assessment and Enhancement in Autonomous Systems

Jenihhin, Maksim, Reorda, Matteo Sonza, Balakrishnan, Aneesh, Alexandrescu, Dan

Year:

2019

Language:

english

File:

PDF, 584 KB

english, 2019

42

[IEEE 2019 IEEE International Test Conference in Asia (ITC-Asia) - Tokyo, Japan (2019.9.3-2019.9.5)] 2019 IEEE International Test Conference in Asia (ITC-Asia) - Test-Plan Optimization for Flying-Probes In-Circuit Testers

Bonaria, Luciano, Raganato, Maurizio, Squillero, Giovanni, Reorda, Matteo Sonza

Year:

2019

File:

PDF, 222 KB

2019

43

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

Carlo, Stefano Di, Condia, Josie E. Rodriguez, Reorda, Matteo Sonza

Journal:

Year:

2020

File:

PDF, 3.18 MB

2020

44

FlexGripPlus: An improved GPGPU model to support reliability analysis

Condia, Josie E. Rodriguez, Du, Boyang, Sonza Reorda, Matteo, Sterpone, Luca

Journal:

Microelectronics Reliability

Year:

2020

File:

PDF, 1.86 MB

2020

45

[IEEE 2020 IEEE 38th VLSI Test Symposium (VTS) - San Diego, CA, USA (2020.4.5-2020.4.8)] 2020 IEEE 38th VLSI Test Symposium (VTS) - In-field Functional Test of CAN Bus Controllers

Cantoro, Riccardo, Sartoni, Sandro, Reorda, Matteo Sonza

Year:

2020

File:

PDF, 116 KB

2020

46

Improving GPU register file reliability with a comprehensive ISA extension

GonÃ§alves, M.M., Condia, J.E. Rodriguez, Reorda, M. Sonza, Sterpone, L., Azambuja, J.R.

Journal:

Microelectronics Reliability

Year:

2020

File:

PDF, 508 KB

2020

47

Expressing logical and temporal conditions in simulation environments: TPDL∗

Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda

Journal:

Microprocessing and Microprogramming

Year:

1989

Language:

english

File:

PDF, 753 KB

english, 1989

48

Assessing the diagnostic power of test pattern sets

P. Camurati, A. Lioy, P. Prinetto, M.Sonza Reorda

Journal:

Microprocessing and Microprogramming

Year:

1990

Language:

english

File:

PDF, 462 KB

english, 1990

49

A transputer-based gate-level fault simulator

G. Cabodi, S. Gai, M. Sonza Reorda

Journal:

Microprocessing and Microprogramming

Year:

1990

Language:

english

File:

PDF, 418 KB

english, 1990

50

Efficient analysis of single event transients

M. Sonza Reorda, M. Violante

Journal:

Journal of Systems Architecture

Year:

2004

Language:

english

File:

PDF, 280 KB

english, 2004

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